PCIe
The high-speed slot standard that connects GPUs, NVMe drives, and other expansion cards to your motherboard. Each generation roughly doubles the bandwidth of the last.
PCIe (Peripheral Component Interconnect Express) is the serial bus that links your GPU, NVMe SSD, and other add-in cards to the CPU and system memory. For local AI rigs, it's the pipe every token has to cross when data moves between VRAM and host RAM.
Generations and Lane Counts
PCIe is specified by generation (3.0, 4.0, 5.0) and lane width (x1, x4, x8, x16). Each generation roughly doubles per-lane bandwidth: PCIe 4.0 x16 delivers around 32 GB/s, PCIe 5.0 x16 around 64 GB/s. The RTX 5060 Ti, for example, runs on a PCIe 5.0 x8 slot — half the lanes of a flagship card, but the newer generation keeps total bandwidth competitive with PCIe 4.0 x16. Lower-end boards and small form factors like Raspberry Pi expose only a single PCIe lane, which is fine for a microSD replacement but a non-starter for a discrete GPU.
Slot Layout and Multi-GPU Builds
Motherboard layout decides what you can actually install. Most consumer boards expose one full-bandwidth x16 slot wired to the CPU and one or more secondary slots that drop to x8 or x4 when populated. Dual-GPU local LLM builds live or die on this — that "second PCIe slot collecting dust" next to your RTX 4090 only matters if it's wired with enough lanes and physical clearance for a second 3-slot card. For pure inference, x8 instead of x16 costs almost nothing in tokens per second; for training or tensor-parallel inference, the bandwidth gap starts to bite.
Why It Matters for Local AI
PCIe sets the ceiling on how fast weights, activations, and KV-cache data move between cards and system memory. When a model spills out of VRAM and you start VRAM offloading layers to system RAM, every forward pass pays the PCIe tax — and that's when generation speed collapses. Pick a board with enough lanes for the cards you actually plan to run, not just the one you're starting with.